1. Technical Field
The present invention is related to semiconductor devices, and more particularly, to a valid-transmission verifying circuit for determining whether data has been transmitted to another device within a predetermined time and a semiconductor device including the same.
2. Discussion of the Related Art
Generally, semiconductor devices provide signals or data to another device by way of output pads connected to their output terminals. In this approach, the load between the output pads and another device is typically estimated at a relatively small capacitance value of about 30 pF. When a semiconductor device has such a load between its output pads and another device, a valid-transmission verifying test is carried out to determine whether data output therefrom has been transmitted to another device within a predetermined time.
FIG. 1 is a circuit diagram for describing a valid-transmission test in a conventional semiconductor device. The valid-transmission test is carried out by using a direct transmission test that applies signals or data directly to a test system 20 from a normal output circuit 11 such as an output pad of a semiconductor device 10. In the direct transmission test, the test system 20 receives data or signals from the normal output circuit 11, and verifies that the data or signals are effectively transferred thereto by analyzing the received data or signals.
During this process, various types of parasitic capacitance and resistance between the normal output circuit 11 and the test system 20 are generated. FIG. 1 also illustrates a pattern of the parasitic capacitances and resistances that may be generated. For example, in FIG. 1, Rd and Cd represent resistance and capacitance, respectively, at a test socket. Rp and Cp represent resistance and capacitance, respectively, at a test board. Rt and Ct represent resistance and capacitance, respectively, at a transmission line and Cc represents capacitance at a receiving part of the test system 20.
However, here, the sum of the parasitic capacitance between the test system 20 and the normal output circuit 11 is a relatively large value of about 70 pF. This value is much larger than the estimated capacitance of about 30 pF. As a result, the valid-transmission test must consider speed margins that change due to the parasitic capacitance. Thus, because the valid-transmission test is not capable considering all the differences between the practical and expected values of parasitic capacitance resulting from various testing conditions, the reliability of the test may be greatly affected.
As such, a need exists for a device that is capable of reliably performing a valid-transmission test in a semiconductor device without regard to external testing conditions.